1. Technical Field of the Invention
This invention pertains to inventive methods of manufacturing a semiconductor device for improving device performance, and to the resulting unique high-performance device structure. In particular, this invention has improved charge mobility in FET devices by structurally imposing tensile and compression forces in a device substrate during device fabrication.
Within the field of semiconductor device design, it is known that mechanical stresses within the device substrate can modulate device performance. Individual stress tensor components affect device behavior of PFETs and NFETs differently. Previous improvements that utilized stress enhancements tended to focus on one or the other type of device outside of a practical performance environment, such as in an IC chip. In order to maximize the performance of both PFETs and NFETs within IC chips, the stress components need to be engineered and applied differently, yet simultaneously. The best stress design is tension in both directions for the nFET and compression in the longitudinal direction for the pFET along with tension in the transverse direction relative to channel current. In this invention we show a method and structure by which we can use spacers to introduce a longitudinal tensile stress for the nFET while at the same time applying a longitudinal compressive stress on the pFET device in a conventional FET structure, and selectively deposited layers on silicon-on-insulator (xe2x80x9cSOIxe2x80x9d) structures. The longitudinal stress is induced along the same axis as the current, or charge, being carried in the channel. It may be more difficult to impose a stress in the transverse direction using spacers so we lose benefit from that direction. However, by virtue of the fact that we can move the stress inducing component closer to the device through the use of stress inducing spacers and layers, the modulation of stress can be improved relative to the isolation material or STI stress approach as suggested in the patent application identified above. One advantage of the method and structure of the present invention that it has provided a device performance improvement for both the nFET and pFET simultaneously.
2. Description of the Prior Art
Ito et al (IEDM, 2000) impose stress using an etch-stop nitride superlayer that is deposited after the device is completely constructed. Again, here the films have a built-in intrinsic biaxial stress which they modulated from compressive through tensile. They found that when the film is in tension the nFET performance is enhanced while that of the pFET""s is degraded. They found the reverse for compression, namely NFET is degraded while the pFET is enhanced. They could not improve the performance of both the pFET and nFET simultaneously. Also, since the film is well above the device the stress translated down into the silicon will be somewhat lesser, particularly when compared to material that is adjacent to the device.
In the application identified above entitled xe2x80x9cIsolation Structures for Imposing Stress Patternsxe2x80x9d, we showed how to modulate the stresses imposed on the silicon by isolation (the preferred example used STI). One of the embodiments advocates the use of materials with different intrinsic stress and coefficients of expansion mismatched in the appropriate regions of the nFETs and pFETs to modulate induced stresses. In another embodiment, we discussed how to add compressive stress by oxidation through openings in a nitride liner as needed for pFETs in the longitudinal direction, while retaining all the tensile stresses (in the transverse pFET direction and transverse+longitudinal nFET directions) from intrinsic and thermal mismatch properties. Prior to these two recent disclosures, all prior known solutions and methods using mechanical stress for device performance enhancement improved neither both nFETs and pFETs simultaneously nor taught the individual device isolation structures and methods of making them. In the present specification we leverage stress effects on devices using stress induced by spacers and by processing, e.g. oxidizing, a selectively deposited silicon isolation liner on SOI structures. We also show how to modulate the stresses for both pFETs and nFETs, which brings the stress effect much closer to the device.
In this invention we show methods and structures by which we have applied tensile stress for the NFET while at the same time applying a compressive longitudinal stress on the PFET device. The structures and methods of making each device individually is also unique. Other disclosed embodiments teach structures, and methods of formation, for selectively inducing strain in the channel of pMOSFETs by using a patterned and oxidized isolation liner. Particular embodiments of the present invention rely upon the volume expansion of a patterned and oxidized silicon liner in isolation regions, or spacers on gate sidewalls, to selectively induce appropriate strain in the channels of adjacent pMOSFETs. The oxidized silicon liner induces a bending moment in an SOI island, resulting in a compressive stress centered in the channel. The compressive stress on the longitudinal component of the PFET may be tuned by varying the thickness of the silicon liner or, in another embodiment, structures and methods of formation are illustrated by which patterned and oxidized spacers on the sidewalls of the active area are used to introduce a longitudinal compressive stress on the pFET device. Through the use of patterned oxidized spacers, the stress is applied closer to the device than is possible with STI fill alone, significantly improving the ability to modulate the stress. It is also shown that the structure of the invention has a negligible effect on stress induced on adjacent devices, where stress modification may not be desired.
The primary advantage of these methods and structures is that they have provided device performance improvement. Another advantage is the method for fabricating NFETs and PFETs simultaneously on a common substrate, wherein each device is designed to enhance performance using stress inducing spacers and isolation liners. A secondary advantage is the structure and method of building an individual device with enhanced performance provided via stress inducing spacers and liners.
It is an object of the present invention to provide device performance improvements for NFETs, PFETs, and for both NFETs and PFETs simultaneously. It is another object of the present invention to be readily integratible into present manufacturing processes. It is another object of the present invention to be manufacturable in bulk silicon, silicon-on-insulator (xe2x80x9cSOIxe2x80x9d), and strained silicon structures. It is yet another object of the present invention to provide improved devices that can be integrated into present processes cheaply for significant device performance improvements.
This invention comprises a spacer structure for an NFET device and for a PFET device. A spacer region for the NFET device contains therein a first spacer material which applies a first type of mechanical stress on the NFET device in a longitudinal direction. A spacer region for the PFET device applies an opposing mechanical stress on the PFET device in the same longitudinal direction. The spacer regions may comprise similar or different spacer materials. Typically, the mechanical stresses are either tensile or compressive.
In another aspect, this invention comprises a method for making NFET and PFET devices. This aspect incorporates the formation of spacer regions at the sidewalls of the NFET gate. Another spacer is formed on the sidewalls of the PFET gate. Spacer materials in these spacer regions are selected to apply a first type of mechanical stress on the NFET device in the longitudinal direction (same axis as the direction of the device""s channel current) and another type of mechanical stress on the PFET device in the longitudinal direction.
In another aspect, the present invention comprises source and drain regions formed in a substrate. The substrate having a channel region between each of the source and drain regions. A gate region adjacent the channel region controls conduction through the channel region. Stress inducing spacer material adjacent selected sides of the gate region imparts stress, i.e. tension or compression, to at least the channel region of the substrate.
In another aspect, this invention comprises an IC chip comprising, and a method of making on the IC chip, a plurality of stressed SOI regions and a plurality of unstressed SOI regions for use in FET and/or device manufacturing. FET devices on the IC chip comprise a stress inducing layer only on the ends of the stressed SOI regions. The stress inducing layer is deposited as a separate IC fabrication step. This stress inducing layer is then exposed to a preselected agent, which may be, for example, a gas, that modifies, e.g. expands, the stress inducing layer which then propagates a longitudinal mechanical stress in the SOI regions.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.